1. Field of the Invention
This invention relates to methods used for the fabrication of semiconductor devices, and more specifically to processes used to create vias between interconnect metallization levels.
2. Description of the Prior Art
The semiconductor industry is continually striving to improve the performance of semiconductor devices, while still attempting to reduce the cost of these same devices. These objectives have been partially achieved by the trend to micro-miniaturazation, or the ability to produce semiconductor devices with sub-micron features. Significant advances in specific semiconductor fabrication disciplines, such as photolithography and reactive ion etching, have allowed micro-miniaturization to occur. More sophisticated exposure cameras, as well as the development of more sensitive photoresist materials, have allowed sub-micron images to be created in photoresist layers. Similar advances in the dry etching discipline has resulted in the sub-micron images, in photoresist, in photoresist, being successfully defined in underlying materials, that are used for the fabrication of semiconductor devices.
The use of sub-micron features, can however, create new concerns, not encountered with devices fabricated with less aggressive groundrules. For example in order to maintain the conductivity requirement for sub-micron metal interconnects, the metal lines have to be thicker than for wider metal interconnect counterparts. In addition, the spaces between metal interconnects also decreases, subsequently resulting in difficulties when conventional passivation processes are used to fill these narrow spaces. Another area of concern is via formation, used to connect two levels of metal interconnects. Narrower via holes, used for sub-micron metallization processes, are more difficult to fill with the via metallization, than wider via counterparts that were previously used. These new problems, encountered when using sub-micron technologies, have been addressed. For example Allman, et al, in U.S. Pat. No. 5,312,512, and Fisher, et al, in U.S. Pat. No. 4,917,759, have described methods for filling narrow spaces between metal interconnects. However this invention will teach a fabrication sequence that allows a more complete solution for creation sub-micron vias, using a metal pillar approach, as well as an optimized process for filling the narrow spaces between the metal pillar vias.